Designing a modern chip at 5nm costs over $500 million and takes hundreds of engineers two to three years. Cadence’s ChipStack Super Agent Platform is the semiconductor industry’s first attempt to change those numbers with agentic AI: a system where AI agents don’t just optimize individual steps but plan, execute, and coordinate the entire design flow from RTL to GDSII. Ten of the world’s largest chipmakers, including NVIDIA, Qualcomm, and Samsung, are already running it on production designs.
ChipStack isn’t a chatbot bolted onto existing tools. It’s a three-layer agentic system: a Super Agent that decomposes complex design goals into plans, domain-specific Task Agents that execute those plans, and an Agent Fabric that ties everything together with foundation models and proprietary semiconductor data. The claim: 10x more automation of the IC design workflow compared to what exists today.
Why Chip Design Needs Agentic AI Now
The semiconductor industry has a math problem. According to Bloomberg, the global chip design market hit $24 billion in 2025, but the supply of engineers who can actually do the work is shrinking. About 53% of semiconductor firms report difficulty recruiting professionals with advanced EDA expertise, and the U.S. alone faces an estimated shortage of 23,000 design engineers by 2030.
Meanwhile, chip complexity keeps climbing. A modern SoC at an advanced node can contain tens of billions of transistors. The traditional workflow is painfully sequential: an engineer runs a synthesis tool, reviews results, adjusts parameters, runs place-and-route, checks timing, iterates, runs signoff, finds violations, goes back three steps. Each handoff between tools is a potential bottleneck where tribal knowledge matters more than documentation.
This is precisely the type of problem agentic AI was built for. Not replacing engineers, but automating the tedious, repetitive orchestration between tools so that human expertise focuses on architecture decisions rather than parameter tuning.
ChipStack’s Three-Layer Architecture
What makes ChipStack different from previous AI-in-EDA attempts (like Cadence’s own Cadence.AI portfolio or Synopsys DSO.ai) is the scope. Earlier systems optimized individual steps. ChipStack orchestrates entire flows.
The Super Agent: Planner and Coordinator
The Super Agent sits at the top. You give it a high-level design goal, something like “optimize this block for power at 3nm while meeting timing at 1.2 GHz,” and it decomposes that into a structured execution plan. It decides which tools to run, in what order, with what parameters, and it adjusts the plan based on intermediate results.
Think of it as the staff engineer who knows the entire design flow and can coordinate between the logic design team, the physical design team, and the signoff team. Except it doesn’t take vacation and it has perfect recall of every design parameter it has ever seen.
Task Agents: Domain Specialists
Below the Super Agent are pre-verified Task Agents that cover specific domains: logic design, physical design, signoff, and verification. Each Task Agent has deep knowledge of its domain’s tools and constraints. The physical design Task Agent, for example, knows Cadence Innovus inside and out: what settings affect routability, how to balance congestion against timing, when to run incremental optimization versus a full re-run.
The “pre-verified” part matters. These aren’t general-purpose LLM agents that hallucinate tool flags. They have been validated against Cadence’s own tool documentation and design rules. When a Task Agent suggests running a specific ECO flow, it knows the exact command syntax and expected output.
Agent Fabric: The Intelligence Layer
The Agent Fabric is the platform underneath that connects everything. It integrates foundation models (likely fine-tuned LLMs) with domain-specific context, Cadence’s proprietary semiconductor design data, and each customer’s own IP and design collateral. This is where ChipStack’s competitive moat lives: decades of Cadence tool data and design knowledge encoded into a system that no general-purpose AI can replicate.
According to EE Times, this shift represents a move from “tool-centric” to “goal-centric” design. Engineers stop thinking about which tool to run next and start thinking about what outcome they want.
Who’s Using ChipStack (and What They’re Saying)
The customer list reads like a semiconductor hall of fame. Ten companies confirmed deployment or collaboration at launch:
NVIDIA is running ChipStack on its “most advanced chip design programs.” Gary Brown, VP of Physical Design and Signoff EDA at NVIDIA, told Cadence the agents are “driving impressive productivity gains” by understanding the full depth of Cadence’s EDA tools.
Qualcomm CTO Q Hommes said ChipStack has “potential to reshape how we approach complex chip design” and that they’re “already seeing results.”
Telechips is using it for their Dolphin5, an AI-native autonomous driving chipset, which is one of the more specific and revealing use cases. This is safety-critical silicon where design correctness is non-negotiable.
Samsung Electronics is collaborating with Cadence on deploying ChipStack at advanced foundry nodes, aiming to help its foundry customers design chips faster. SK hynix, MediaTek, Realtek, Renesas, Altera (Intel), and AMD round out the confirmed partners.
Notice the language: most companies say “initial results” or “potential.” This is a new platform. The 10x automation claim is about coverage of the workflow, not a 10x speed improvement on day one.
Cadence vs. Synopsys: The EDA AI Arms Race
You can’t discuss ChipStack without mentioning Synopsys DSO.ai, which has been the biggest name in AI-for-EDA since its launch. The two companies split the EDA market almost evenly: Synopsys at roughly 31% market share, Cadence at 30%.
DSO.ai operates as an autonomous optimization agent within individual tools. It searches massive solution spaces to find optimal power, performance, and area (PPA) tradeoffs. Synopsys claims tasks that once took five engineers and three weeks can be completed in five hours with DSO.ai. That’s real, validated by multiple customers.
But DSO.ai optimizes within a single tool or a single step. ChipStack’s pitch is orchestration across the entire flow. Synopsys is responding: at DAC 2025, they previewed AgentEngineer, their own multi-agent system built on a partnership with Microsoft. Their roadmap goes from single-agent step-level actions (L2) to complex multi-agent actions (L3) to dynamic flow optimization (L4) to fully autonomous decision-making (L5).
| Feature | Cadence ChipStack | Synopsys DSO.ai / AgentEngineer |
|---|---|---|
| Scope | Full RTL-to-GDSII orchestration | Step-level optimization (DSO.ai); multi-agent planned (AgentEngineer) |
| Architecture | Super Agent + Task Agents + Agent Fabric | Autonomous search agent (DSO.ai); AgentEngineer in preview |
| Customers | 10 named at launch | Hundreds using DSO.ai; AgentEngineer early access |
| Maturity | Launched April 2025 | DSO.ai launched 2020; AgentEngineer in prototype |
The honest assessment: Cadence has a more ambitious architecture today, but Synopsys has years of production data from DSO.ai. The winner will be whoever delivers measurable PPA improvements, not whoever has the most impressive slide deck.
What “10x Automation” Actually Means
Cadence’s 10x claim deserves scrutiny. They’re not claiming chips get designed 10x faster. They’re claiming ChipStack automates 10x more of the design workflow compared to previous approaches.
The difference matters. If a traditional flow requires 100 manual intervention points, and existing AI tools automate 5 of them, automating 50 would be a 10x improvement in automation coverage. That could translate to significant time and cost savings, but the relationship isn’t linear. Some of those 50 newly automated steps might be quick, while the remaining 50 manual ones might be the hardest.
The EDA market is projected to hit $34.7 billion by 2035, growing at a pace that suggests the industry believes AI-driven automation is real, not just marketing. With chip design costs at advanced nodes running into hundreds of millions of dollars, even a 20% reduction in engineering time pays for itself many times over.
For engineering managers, the question isn’t whether to adopt AI-driven EDA tools. It’s which platform locks you in less. Cadence and Synopsys each want you on their respective stacks. The tools are powerful, but switching costs are real.
Frequently Asked Questions
What is Cadence ChipStack?
Cadence ChipStack is the semiconductor industry’s first agentic AI platform purpose-built for IC design. It uses a three-layer architecture: a Super Agent that plans and coordinates, domain-specific Task Agents for logic, physical design, and signoff, and an Agent Fabric that integrates foundation models with proprietary semiconductor data. The goal is automating the full chip design workflow from RTL to GDSII.
How does ChipStack differ from Synopsys DSO.ai?
DSO.ai optimizes individual steps within the chip design flow, searching for optimal PPA within a single tool. ChipStack orchestrates the entire design flow using a multi-agent system where a Super Agent coordinates domain-specific Task Agents. Synopsys is developing AgentEngineer as its own multi-agent response to ChipStack.
Which companies use Cadence ChipStack?
Ten major semiconductor companies confirmed deployment or collaboration at launch: NVIDIA, Qualcomm, Samsung Electronics, AMD, Altera (Intel), SK hynix, MediaTek, Realtek, Renesas, and Telechips. NVIDIA is running it on its most advanced chip design programs.
Does ChipStack replace human chip designers?
No. ChipStack maintains a human-in-the-loop approach where engineers set high-level design goals and retain oversight. AI agents handle the repetitive orchestration, parameter tuning, and multi-step workflow execution. Engineers focus on architecture decisions and reviewing agent outputs.
What does Cadence mean by 10x automation?
Cadence claims ChipStack automates up to 10x more of the IC design workflow compared to previous approaches. This is about coverage of automated steps, not a 10x speed improvement. The actual time savings depend on which steps are automated and how complex the remaining manual ones are.